Robust signaling techniques for through silicon via bundles

In high performance 3D ICs with increasing trend for multi-core and NoC architectures, signaling techniques play a crucial role in determining the overall performance of the system. In this work, we explored single ended and differential signaling techniques for Through Silicon Via (TSV) bundles and analyzed their behavior in the presence of power supply noise. We obtained maximum data rate and energy/bit values for each of the signaling techniques and identified the dominant factors that determine these values. Simple analysis is carried out to understand the impact of fault tolerant scheme on the performance of the signaling technique. Frequency dependent RLGC parasitics of 3x3 and 4x4 TSV bundles are extracted using Ansoft Q3D Extractor. NCSU 45nm PDK and HSPICE simulation tool are used. For robustness to supply noise analysis, noise amplitudes of 2.5%, 5%, 7.5% and 10% of supply voltage and a noise frequency of 200MHz is considered. It is observed that Inter Symbol Interference (ISI), power supply noise and fault tolerant architecture play crucial role in determining the robust and high performance signaling technique for TSV bundles.