The effect of page allocation on caches

Medium to large physically-indexed low-associativity caches, where physical page number bits index the cache, present two problems. First, cache miss rate varies between runs, as data location in the cache depends on the placement of virtual pages in physical memory. Secondly, the virtual-to-physical address translation must precede cache indexing, increasing latency. This paper summarizes simulation results of instruction, data, and unified caches with conventional page allocation, and explores improving the mean miss rate by controlling (coloring) page allocation. A more strict page coloring algorithm reduces latency by allowing cache indexing to precede address translation.