A comprehensive instruction fetch mechanism for a processor supporting speculative execution

A superscalar processor supporting speculative ex ecution requires an instruction fetch mechanism that can provide instruction fetch addresses as nearly cor rect as possible and as soon as possible in order to re duce the likelihood of throwing away speculative work In this paper we propose a comprehensive instruction fetch mechanism to satisfy that need Implementation issues are identi ed possible solutions and designs for resolving those issues are simulated and the results of these simulations are presented A metric for mea suring the average penalty of executing a branch in struction is introduced and used to evaluate the per formance of our instruction fetch mechanism We achieve an average performance of IPC on the original SPEC benchmarks in a machine which can execute ve instructions ideally by using the proposed mechanism