Y-Pipe: a conditional branching scheme without pipeline delays

The “Y-Pipe” is a hardware conditional branching scheme that allows pipelined processors to perform conditional branches without any pipeline delays. The essence behind the Y-Pipe is the duplication of all pipeline stages before the execution stage of the pipeline. Given a scalar processor, under normal operations both paths are fetching and decoding the same instruction. After encountering a COMPAREBRANCH instruction structure, the two paths in the Y-pipe will start fetching and decoding separate instructions. The scheme will work for consecutive COMPAREBRANCH instruction structures. The Y-Pipe scheme has been simulated and compared against using the delayed branching scheme. The results show that the p r e posed Y-pipe scheme incurs no branch delays and provides 100% branch prediction.