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Interconnect design considerations for large NUCA caches
Author(s) -
Naveen Muralimanohar,
Rajeev Balasubramonian
Publication year - 2007
Publication title -
acm sigarch computer architecture news
Language(s) - Uncategorized
Resource type - Journals
eISSN - 1943-5851
pISSN - 0163-5964
DOI - 10.1145/1273440.1250708
Subject(s) - cache , computer science , cache algorithms , cache pollution , smart cache , bottleneck , parallel computing , cache invalidation , cache coloring , interconnection , computer architecture , cpu cache , embedded system , computer network

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