Flexible Hardware Reduction for Elliptic Curve Cryptography in GF(2m)

This paper discuss two ways to provide flexible hardware support for the reduction step in elliptic curve cryptography in binary fields (GF(2m)). In the first approach the authors are using several dedicated reduction units within a single multiplier. The measurement results show that this simple approach leads to an additional area consumption of less than 10% compared to a dedicated design without performance penalties. In the second approach any elliptic curve cryptography up to a predefined maximal length can be supported. Here the authors take advantage of the features of commonly used reduction polynomials. The results show a significant area penalty compared to dedicated designs. However, the authors achieve flexibility and the performance is still significantly better than those of known ECC hardware accelerator approaches with similar flexibility or even software implementations