Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology | Zendy

Peng Song | Zendy; Rajit Manohar | Zendy

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Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology

Author(s) -

Peng Song,

Rajit Manohar

Publication year - 2006

Publication title -

citeseer x (the pennsylvania state university)

Language(s) - English

Resource type - Conference proceedings

ISBN - 1-59593-347-6

DOI - 10.1145/1127908.1127947

Subject(s) - asynchronous communication , control reconfiguration , asynchronous circuit , computer science , logic synthesis , spare part , electronic circuit , planar , logic gate , electronic engineering , computer architecture , yield (engineering) , combinational logic , graph , embedded system , electrical engineering , engineering , theoretical computer science , algorithm , materials science , telecommunications , synchronous circuit , clock signal , metallurgy , mechanical engineering , computer graphics (images)

This paper presents a systematic design for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the target asynchronous circuits on one planar device layer which is fabricated with aggressive technology, are built on fault tolerant graph models with extra spare resources, and can be reconfigured by autonomous reconfiguration logic on another planar device layer which is fabricated with conservative technology, in the presence of hard errors. The yield analysis shows that this method can result in 20--30% overall yield enhancement. This design methodology can be conveniently applied to clocked designs without significant changes.

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