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Placement for configurable dataflow architecture
Author(s) -
Mongkol Ekpanyapong,
Michael B. Healy,
Sung Kyu Lim
Publication year - 2005
Publication title -
citeseer x (the pennsylvania state university)
Language(s) - English
Resource type - Conference proceedings
ISBN - 0-7803-8737-6
DOI - 10.1145/1120725.1120840
Subject(s) - dataflow , computer science , bottleneck , parallel computing , dataflow architecture , set (abstract data type) , computer architecture , distributed computing , real time computing , embedded system , programming language
As wire delay increasingly becomes a significant performance bottleneck in monolithic architectures, there is a strong motivation to move to Dataflow Architectures. In this paper, we propose a set of placement algorithms for generic dataflow architectures. Our timing-driven and profile-driven placement algorithms respectively are targeting streaming and non-streaming applications. Compared to the conventional wirelength-driven algorithm, our timing-driven placer reduces the longest path delay by 23% and maximum slack by 26% at the cost of 10% increase in wirelength for streaming applications. In addition, our profile-driven placer reduces the total execution time of non-streaming applications by 17%. Lastly, our simultaneous timing/profile-driven placer reduces the total execution time of non-streaming applications by 13% on average.

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