Toward stochastic design for digital circuits - statistical static timing analysis

Due to the process variations and the variations of environmental factors such as supply voltage and temperature, the circuit parameters and hence the circuit performance such as delay fluctuate, and their variability and uncertainty are increasing in the deep sub-micron technology. Therefore, producing high performance digital circuits in high yield becomes difficult more and more. Various efforts have been done in order to analyze and reduce such fluctuations. Among them, statistical static timing analysis has been studied intensively in these days, which finds the distribution of the critical delay when the distribution of the delay of each element in a circuit is given. Such a statistical analysis takes probability into consideration, and is different from the conventional design style treating deterministic values only. Hence, it can be called a stochastic design style, which fits to the concept of the yield. This paper surveys the statistical static timing analysis tools, and considers the expectations of stochastic design. In the deep sub-micron technology, numerous collaborations between design and process will be needed in order to increase the yield and to shorten the time-to-market. Therefore, stochastic design style may open a new vista in the digital circuit design.