Wire length and via reduction for yield enhancement | Zendy

V.K.R. Chiluvuri | Zendy; Israel Koren | Zendy

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<title>Wire length and via reduction for yield enhancement</title>

Author(s) -

V.K.R. Chiluvuri,

Israel Koren

Publication year - 1996

Publication title -

proceedings of spie, the international society for optical engineering/proceedings of spie

Language(s) - English

Resource type - Conference proceedings

SCImago Journal Rank - 0.192

H-Index - 176

eISSN - 1996-756X

pISSN - 0277-786X

DOI - 10.1117/12.250850

Subject(s) - minification , reduction (mathematics) , benchmark (surveying) , yield (engineering) , algorithm , very large scale integration , electronic circuit , set (abstract data type) , routing (electronic design automation) , computer science , mathematics , mathematical optimization , engineering , electrical engineering , materials science , embedded system , geometry , programming language , geodesy , metallurgy , geography

Wire length reduction along with via minimization results in better performance and higher yield for VLSI circuits. In this paper we present a wire length reduction algorithm for channel routing. The results of our algorithm for a set of benchmark examples are presented. The algorithm produces near optimal results for most of the examples. Surprisingly, our algorithm outperforms most of the previously proposed via minimization algorithms as well. Our results show that both wire length and via minimization problems are closely related to each other but their optimal solutions don't necessarily coincide.

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