A 10-b 600-MS/s 2-Way Time-Interleaved SAR ADC With Mean Absolute Deviation-Based Background Timing-Skew Calibration
Author(s) -
Jeonggoo Song,
Kareem Ragab,
Xiyuan Tang,
Nan Sun
Publication year - 2019
Publication title -
ieee transactions on circuits and systems i regular papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.861
H-Index - 163
eISSN - 1558-0806
pISSN - 1549-8328
DOI - 10.1109/tcsi.2019.2907581
Subject(s) - skew , calibration , comparator , detector , standard deviation , algorithm , cmos , figure of merit , mathematics , computer science , convergence (economics) , electronic engineering , statistics , electrical engineering , voltage , engineering , telecommunications , economic growth , economics , computer vision
This paper presents a mean absolute deviation (MAD)-based background timing-skew calibration technique for time-interleaved (TI) ADCs. It uses a single comparator-based window detector to select input samples near the zero crossing and computes their MAD value, which is used as an indicator for the timing skew. The proposed technique has low computation complexity, as it only requires taking absolute value and averaging. It also has a fast convergence speed when operating in the background with unknown random inputs, as the MAD value can be accurately estimated with a small number of samples. A prototype 10-bit 2-way TI-SAR ADC is built in 40-nm CMOS to verify the proposed technique. It achieves over 52 dB of SNDR over the entire Nyquist band. Operating at 600 MS/s, it consumes 4.7 mW, which translates to a Walden figure-of-merit of 24-fJ/conversion-step.
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