Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs | Zendy

Xiaohong Chen | Zendy; Kai Ni | Zendy; Michael Niemier | Zendy; Yinhe Han | Zendy; Suman Datta | Zendy; Xiaobo Sharon Hu | Zendy

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Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs

Author(s) -

Xiaohong Chen,

Kai Ni,

Michael Niemier,

Yinhe Han,

Suman Datta,

Xiaobo Sharon Hu

Publication year - 2018

Publication title -

ieee transactions on circuits and systems i regular papers

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.861

H-Index - 163

eISSN - 1558-0806

pISSN - 1549-8328

DOI - 10.1109/tcsi.2018.2874880

Subject(s) - non volatile memory , field programmable gate array , routing (electronic design automation) , resistive random access memory , cmos , computer science , transistor , electronic engineering , electrical engineering , embedded system , computer hardware , engineering , voltage

As an emerging nonvolatile device, ferroelectric field-effect transistors (FeFETs) have the potential to reduce the power and area by integrating nonvolatile storage elements with logic. The hysteretic behavior allows an FeFET to function as both a nonvolatile storage element and a switch. This paper exploits this feature of FeFETs to design lookup tables (LUTs) and routing switches, which have ob...

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