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Asynchronous Ballistic Reversible Fluxon Logic
Author(s) -
Michael P. Frank,
Rupert Lewis,
Nancy A. Missert,
Matthäus A. Wolak,
Michael David Henry
Publication year - 2019
Publication title -
ieee transactions on applied superconductivity
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.467
H-Index - 84
eISSN - 1558-2515
pISSN - 1051-8223
DOI - 10.1109/tasc.2019.2904962
Subject(s) - fluxon , asynchronous communication , josephson effect , physics , computer science , condensed matter physics , superconductivity , josephson energy , telecommunications
In a previous paper, we described a new abstract circuit model for reversible computation called asynchronous ballistic reversible computing (ABRC), in which localized information-bearing pulses propagate ballistically along signal paths between stateful abstract devices and elastically scatter off those devices serially, while updating the device state in a logically-reversible and deterministic fashion. The ABRC model has been shown to be capable of universal computation. In the research reported here, we begin exploring how the ABRC model might be realized in practice using single flux quantum solitons (fluxons) in superconducting Josephson junction (JJ) circuits. One natural family of realizations could utilize fluxon polarity to represent binary data in individual pulses propagating near-ballistically, along discrete or continuous long Josephson junctions or microstrip passive transmission lines, and utilize the flux charge (−1, 0, +1) of a JJ-containing superconducting loop with Φ0 < IcL < 2Φ0 to encode a ternary state variable internal to a device. A natural question then arises as to which of the definable abstract ABRC device functionalities using this data representation might be implementable using a JJ circuit that dissipates only a small fraction of the input fluxon energy. We discuss conservation rules and symmetries considered as constraints to be obeyed in these circuits, and begin the process of classifying the possible ABRC devices in this family having up to three bidirectional I/O terminals, and up to three internal states.

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