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Network-on-chip has been proposed as an alternative to bus-based system to achieve high performance and scalability. The topology of on-chip interconnect plays a crucial role in system on chip performance, energy, and area requirements. In this paper, an on-chip interconnects architecture based on WK-recursive network is proposed. WK-recursive structure is analyzed and compared to 2D mesh and Spidergon structures. Simulation results show that WK-recursive on-chip interconnect generally outperforms the other architectures.

Simulation and Evaluation of On-Chip Interconnect Architectures: 2D Mesh, Spidergon, and WK-Recursive Network