Low Power SRAMs for Battery Operation

In recent years, a growing class of personal computing devices has emerged including portable desktops, digital pens, and new audio- and video-based multimedia products. Other new products include wireless communications and imaging systems such as personal digital assistants, personal communicators and smart cards. These devices and systems demand high-speed, high-throughput computations, complex functionalities and often real-time processing capabilities. A key challenge is that the performance of these devices is limited by the size, weight and lifetime of batteries. Battery-operated applications demand new design approaches and methodologies that produce more power-efficient designs, which means significant reductions in power consumption for the same level of performance. Memories such as static random-access memories (SRAMs) contribute to the total system power consumption by up to 50% [1]. This tutorial presentation focuses on critical concepts and circuit techniques that result in significant savings of active and standby power in SRAMs. The topics covered in this tutorial include the following: a brief overview of SRAM architecture and operation; sources of active and standby power dissipation in SRAMs; capacitance reduction techniques; AC and DC power reduction techniques; pulse operation techniques; operating voltage scaling and low-power sensing; and leakage current suppression.