Barra: A Parallel Functional Simulator for GPGPU | Zendy

Caroline Collange | Zendy; Marc Daumas | Zendy; David Defour | Zendy; David Parello | Zendy

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Barra: A Parallel Functional Simulator for GPGPU

Author(s) -

Caroline Collange,

Marc Daumas,

David Defour,

David Parello

Publication year - 2010

Publication title -

2010 ieee international symposium on modeling, analysis and simulation of computer and telecommunication systems

Language(s) - English

Resource type - Conference proceedings

eISSN - 2375-0227

pISSN - 1526-7539

ISBN - 978-1-4244-8181-1

DOI - 10.1109/mascots.2010.43

Subject(s) - computing and processing , communication, networking and broadcast technologies

We present Barra, a simulator of Graphics Processing Units (GPU) tuned for general purpose processing (GPGPU). It is based on the UNISIM framework and it simulates the native instruction set of the Tesla architecture at the functional level. The inputs are CUDA executables produced by NVIDIA tools. No alterations are needed to perform simulations. As it uses parallelism, Barra generates detailed statistics on executions in about the time needed by CUDA to operate in emulation mode. We use it to understand and explore the micro-architecture design spaces of GPUs.

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