Open AccessHierarchical Value Cache Encoding for Off-Chip Data Bus
Author(s) -
Chung-Hsiang Lin,
Chia-Lin Yang,
Ku-Jei King
Publication year - 2006
Publication title -
ntur (臺灣機構典藏)
Language(s) - Uncategorized
Resource type - Conference proceedings
DOI - 10.1109/lpe.2006.4271824
Subject(s) - computer science , cache , system bus , chip , system on a chip , local bus , address bus , embedded system , cache pollution , back side bus , computer hardware , encoding (memory) , value (mathematics) , parallel computing , cpu cache , cache algorithms , control bus , telecommunications , machine learning , artificial intelligence
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