Sub-nW Wake-Up Receivers With Gate-Biased Self-Mixers and Time-Encoded Signal Processing | Zendy

Vivek Mangal | Zendy; Peter R. Kinget | Zendy

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Sub-nW Wake-Up Receivers With Gate-Biased Self-Mixers and Time-Encoded Signal Processing

Author(s) -

Vivek Mangal,

Peter R. Kinget

Publication year - 2019

Publication title -

ieee journal of solid-state circuits

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 2.571

H-Index - 215

eISSN - 1558-173X

pISSN - 0018-9200

DOI - 10.1109/jssc.2019.2941010

Subject(s) - baseband , cmos , latency (audio) , sensitivity (control systems) , offset (computer science) , electronic engineering , electronic circuit , electrical engineering , radio receiver design , power consumption , dbm , dc bias , power (physics) , computer science , engineering , transmitter , physics , voltage , amplifier , channel (broadcasting) , quantum mechanics , programming language

A fully integrated wake-up receiver in 65-nm low-power (LP) CMOS technology is presented. The receiver’s RF front end consists of a 40-stage MOS self-mixer using gate biasing to optimize the sensitivity; the baseband circuits use time-encoded analog signals to efficiently implement a matched filter with a DC offset cancellation loop at minimal power consumption. When operating at 434 MHz, the receiver has a −79.1-dBm sensitivity with a 110-ms latency while consuming 420 pW from 0.4 V. When operating at 1.016 GHz with the same latency, the sensitivity is −74 dBm and power consumption is 470 pW.

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