Open AccessA 78.5-dB SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating Up to 75 MS/s With 24.9-mW Power Consumption in 65-nm CMOS
Author(s) -
Hongda Xu,
Hai Huang,
Yongda Cai,
Ling Du,
Yuan Zhou,
Benwei Xu,
D. Gong,
J. Ye,
Yun Chiu
Publication year - 2018
Publication title -
ieee journal of solid-state circuits
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 2.571
H-Index - 215
eISSN - 1558-173X
pISSN - 0018-9200
DOI - 10.1109/jssc.2018.2879942
Subject(s) - spurious free dynamic range , successive approximation adc , comparator , 12 bit , computer science , cmos , electronic engineering , preamplifier , dynamic range , capacitor , voltage , amplifier , electrical engineering , engineering
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