High-speed I/Os and PLLs for data communication applications

The wireline communication industry is working on the communication systems with data rates of beyond 10 Gb/s. Mixed-signal circuits are required to transmit and receive Gb/s signals over high-speed serial interfaces, and to synthesize and recover GHz clocks, typically using phase-locked loop circuitry. This tutorial will start with setting up a system environment for high-speed serial link applications. Long-haul and metropolitan area networks undergoing transition from OC-48 (2.488 Gb/s) to OC-192 (9.953 Gb/s or 10.7 Gb/s using forward error correction) will be discussed. Upgrades of local area networks (LANs) from 1.25 Gb/s to 10.3 Gb/s Ethernet I/Os are mentioned. Movement of disk drives and storage area networks (SANs) to 10.5 Gb/s Fibre Channel interfaces is described. A brief overview of chip to chip data transfer schemes follows, with an emphasis on the serial I/O. Then fundamentals of phase-locked loop (PLL) design will be discussed. First, the overall system specification for (charge-pump based) PLL systems is presented. Openand closed-loop PLL transfer functions are briefly reviewed. Loop stability and jitter sources are discussed. Design issues for circuit blocks like voltagecontrolled oscillators (VCOs), phase-frequency detectors (PFDs) and charge pumps are discussed. Key PLL based systems, e.g., Clock Synchronizer and Clock/Data Recovery (CDR), are described. The tutorial ends with discussion and design issues of output driver and receiver input blocks of serial links. Pre-emphasis and equalization concepts are described. Implementation schemes for I/O termination and ESD protection are discussed.