Integrating Boundary Scan into Multi-GHz I/O Circuitry

A minimally invasive solution for adding boundary scan to high-speed I/O circuits is described. The insertion of boundary scan registers on the transmit side is done in the lower-speed parallel domain, while the boundary scan registers on the receive side is done using the techniques described in IEEE Std 1149.6 in the high-speed serial domain. Special clocking requirements are described, and results from actual silicon testing are presented that demonstrate negligible impact on functional performance while maintaining compliance with the both 1149.1 and 1149.6 standards.