IEEE Std 1149.6 Implementation for a XAUI-to-Serial 10-Gbps Transceiver

The design, implementation and verification of IEEE Std 1149.6 IP for a transceiver manufactured with 90 nm technology and using Current Mode Logic (CML) are challenging because (i) CML has high operating frequency, (ii) CML has very low operating voltage range, and (iii) CML is inherently a differential type of circuitry. This paper describes how major building blocks of IEEE Std 1149.6 IP-such as input test receiver, boundary scan register containing new AC boundary scan cells, output test signal generation circuitry, and modified TAP controller-were implemented and verified. Third-party CAD tools typically used for IEEE Std 1149.1 IP generation were used for this implementation.