I/O Self-Leakage Test

This paper presents the implementation of the Self- Leakage Test, a new approach for unconnected I/O leakage testing. It provides a path for leakage current through the on-chip leakers and uses the voltage drop at the pad to detect a pass/fail condition. A detailed methodology for defining the self-leakage test specifications has been developed. Preliminary silicon data shows that selfleakage test methodology provide a viable method for high-volume monitoring of I/O leakage at minimal on-die DFT (Design-For-Test) overhead.