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This work summarizes the design for test (DFT) circuitry and test methods that enabled Intel to shift away from traditional functional testing of I/O's. This shift was one of the key enablers for automatic test equipment (ATE) re-use and the move to lower capability (& cost) structural test platforms. Specific examples include circuit implementations from the Pentium/sup /spl reg// 4 processor, high volume manufacturing (HVM) data, and evolutionary changes to address key learnings. We close with indications of how this can be extended to cover the next generation high speed serial like interfaces.

Elimination of traditional functional testing of interface timings at Intel