DETECTING FAULTS IN THE PERIPHERAL CIRCUITS AND AN EVALUATION OF SRAM TESTS

Very little has been published on faults in the memory peripheral circuits, denoted as PFs'. This paper shows that PFs will be detected by march tests, provided that they satisfy particular properties, expressed in terms of properties of the algorithm, and of properties of the algorithm stress. The latter consists of the used data backgrounds and addressing directions. The detection capabilities of a set of well-know march algorithms will be established for the PFs. In addition, industrial results from applying this set of tests to a large number of 0.13 micron 512 Kbyte SRAM chips, combined with a variety of stress conditions, will be presented.