A Hierarchical DFT Architecture for Chip, Board and System Test/Debug

This paper presents the Procket DFT architecture which is developed to improve manufacturability (time-to-market, high quality and ease of chip/board/system bring-up) thus reducing the time for chip ramp and initial system bring-up. Common DFT structures are used on all chips in the family and a similar process is used to access all on-chip DFT structures from the system. This architecture allows for reconfigurable scan chains, which includes parallel chains for tester access, and various sections of the chains during board/system bring up to allow for easy diagnosis. Access to all debug features is via the IEEE 1149.1 ports which allows the same software to be used for chip, board and system debug.