Logic BISTWith Scan Chain Segmentation

This paper presents a novel BIST (Built-In Self Test) scheme with scan chain segmentation. In the scheme, a com- bination of pseudo random patterns and single-weight pat- terns have been applied to CUT (Circuit Under Test). Scan chain is partitioned into multiple segments delimited by in- verters. When a single weighted pattern is applied to a seg- mented scan chain, successive segments receive bit patterns with complementary weights. Several segment configura- tions may be required to achieve full fault coverage. In this scheme the control logic is inside the scan path and built-in self test can be implemented without compromising timing performance of CUT. Experiments show that our scheme can obtain very good fault coverage. Hardware implemen- tation is simple and straightforward.