Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations

A new six transistor (6T) FinFET static memory cell with dynamic access transistor threshold voltage tuning is evaluated in this paper for statistical power and stability distributions under process parameter variations. The independent-gate (IG) FinFET SRAM cell activates only one gate of the double-gate data access transistors during a read operation. The disturbance caused by the direct data access mechanism of the standard 6T SRAM cell topology is significantly reduced by dynamically increasing the threshold voltage of the access transistors. All the transistors in the presented SRAM cell are sized minimum without producing any data stability concerns. The average read static-noise-margin of the statistical samples with the independent gate bias technique is 82% higher as compared to the standard tied-gate FinFET SRAM cells under process variations. Furthermore, the IG-FinFET SRAM circuit reduces the average leakage power and the cell area by up to 53.3% and 17.5%, respectively, as compared to the standard tied-gate FinFET SRAM circuits sized for comparable data stability in a 32 nm FinFET technology.