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In this paper dual-K (DKCMOS) technology is proposed as a method for gate leakage power reduction. An integer linear programming (ILP) based algorithm is proposed for its optimization during architectural synthesis. The algorithm uses device-level gate leakage models for precharacterizing register-transfer level (RTL)datapath component library and minimizes the leakage delay product (LDP). The proposed algorithm is tested for several circuits for 45nm CMOS technology node. The experiments show that average gateleakage reduction are 67.7% and 80.8% for SiO_2-SiON and SiO_2-Si_3N_4, respectively.

ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis