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On Chip Jitter Measurement through a High Accuracy TDC
Author(s) -
Akhil Garg,
Prashant Dubey
Publication year - 2008
Publication title -
9th international symposium on quality electronic design (isqed 2008)
Language(s) - English
DOI - 10.1109/isqed.2008.68
In High speed applications, ratio of total jitter to clock period is critical. It necessitates accurate measurement of Jitter. In this paper we describe an on-chip methodology to measure jitter in time domain, with resolutions up to 0.1ps.

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