Embedded Deterministic Test Exploiting Care Bit Clustering and Seed Borrowing
Author(s) -
Adam B. Kinsman,
Nicola Nicolici
Publication year - 2008
Publication title -
9th international symposium on quality electronic design (isqed 2008)
Language(s) - English
DOI - 10.1109/isqed.2008.65
Embedded deterministic test is a manufacture test paradigm that combines the compression advantage of built-in self-test with the high fault coverage of deterministic stimuli, inherent to methods based on automatic test pattern generation and external testers. Despite enabling the use of low-cost testers for rapidly achieving high fault coverage, embedded deterministic test must consciously use the available tester channel bandwidth to ensure non-disruptive scaling to future devices of increased complexity. The focus of this paper is to show how exploitation of care bit clustering in a test set combined with a low cost implementation for on-chip decompressors based on seed borrowing, facilitates an increased utilization of the tester channel bandwidth, and hence improved compression of deterministic stimuli.
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