A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intel's Test Chips

In the past, it was possible to validate analog CMOS circuits through transistor-level (schematic netlist) simulation. As manufacturing processes grow in complexity, the ever-increasing amount of design-for-test/manufacturability/yield/quality (DFx) circuitry renders transistor-level simulation impractical; and digital behavioral simulation ignores crucial analog interactions. This paper presents a more robust and efficient methodology for pre-silicon validation of such mixed-signal circuits. We adopt a top-down strategy and model all blocks at the behavioral level. However, we also represent select analog blocks at the transistor level. This strategy precludes the need for what is currently a weakness in mixed-signal validation - equivalence checking between analog behavioral models and analog schematics. In addition, this strategy enables performance validation to be seamlessly integrated with functional validation. Further, by leveraging the industry standard languages of SPICE, System Verilog and Verilog-AMS, we are able to build and simulate all modeling and validation constructs with a single tool. On Intel's most recent test chip, our validation methodology found more bugs with fewer person-hours than previous attempts with purely digital or transistor-level validation.