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Summary form only given. Test has long been recognized as the bridge between design and manufacturing. However, innovation and deep integration in design and test tools has not kept pace with the consumerization of electronics and the rapidly evolving nanometer IC design and manufacturing. As a result, the full potential of Test has not been harnessed by the mainstream semiconductor community.The consumerization of electronics places significant new demands on low power, correctness and time-to-volume production.The rapid advances in nanometer technologies pose additional set of challenges due to the advanced physics effects and higher scales of transistor integration. The EDA industry needs to establish a new paradigm and a "deep integration" to meet these challenges. During the design phase, a power-aware DFT architecture must integrate tightly with low power design and implementation flow. Later, during the manufacturing phase, the benefits of DFT must be seamlessly harnessed for rapid scan diagnostics based yield learning using not only logic information from the design database but also using layout timing and power information. This keynote will discuss these challenges and possible solutions and scenarios.

Plenary Speech 2P1: Consumerization of Electronics and Nanometer Technologies: Implications for Manufacturing Test