Towards Gb/s turbo decoding of product code onto an FPGA device

This paper presents the implementation, on an FPGA device of an ultra high rate block turbo code decoder. First, a complexity analysis of the elementary decoder leads to a low complexity decoder architecture (area divided by 2) for a negligible performance degradation. The resulting turbo decoder is implemented on a Xilinx Virtex II-Pro FPGA in a communication experimental setup. Based on an innovative architecture which enables the memory blocks between all half-iterations to be removed and clocked at only 37.5 MHz, the turbo decoder processes input data at 600Mb/s. The component code is an extended Bose, Ray-Chaudhuri, Hocquenghem (eBCH(16,11)) code. Ultra high-speed block turbo decoder architectures meet the demand for even higher data rates and open up new opportunities for the next generations of communication systems such as fiber optic transmissions.