Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules | Zendy

Jhao-Ji Ye | Zendy; You-Gang Chen | Zendy; I-Chyn Wey | Zendy; An-Yeu Wu | Zendy

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Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules

Author(s) -

Jhao-Ji Ye,

You-Gang Chen,

I-Chyn Wey,

An-Yeu Wu

Publication year - 2007

Publication title -

2007 ieee international symposium on circuits and systems (iscas)

Language(s) - English

Resource type - Conference proceedings

eISSN - 2158-1525

pISSN - 0271-4302

DOI - 10.1109/iscas.2007.378044

Subject(s) - components, circuits, devices and systems , communication, networking and broadcast technologies , engineered materials, dielectrics and plasmas

Data transmission on multiple clock domains will face reliable problems. The conventional globally asynchronous locally synchronous (GALS) technique can resolve the problem but has a high latency problem. In this paper, we present a novel asynchronous transmission technique called quasi-synchronous with an adaptive phase mechanism to reduce the transmission latency. Compared with the conventional GALS techniques, the proposed technique saves 50%83% of latency. It is implemented on standard-cell library by using TSMC 0.18um 1P6M CMOS technology.

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