Memory-System Design Considerations for Dynamically-Scheduled Processors

In rhis papeE we identify perjkmance trends and design relationships behveen the following components of the data memory hierarchy in a dynamically-scheduled processor: the register file, the lockup-fee data cache, the stream buffers, and the interface behveen these componentsand the lower levels of the memory hierarchy. Similar pegormance was obtainedfrom all systems having support for freer than four in-fight misses, irrespective of the register-jle size, the issue width of the processoq and the memory bandwidth. While providing support for more than four in-jlight misses did increasesystem performance, the improvementwas less than that obtained by increasing the number of registers. The addition of stream buffers to the investigated systems led to a significant per$ormance increase, with the larger increases for systems having less in-jlight-miss support, greater memory bandwidth, or more instruction issue capability. The perjormance of these sysfems was not signijicantly affected by rhe inclusion of traficjfilters, dynamic-stride calculators, or the inclusion of the per-load nonunity stride-predictor and the incremental-prefetching techniques, which we inmduce. Howevel; the incremental prefetching technique reduces the bandwidth consumed by stream buffers by 50% without a signijicant impact on perfomzance.