Implementing Multidestination Worms In Switch-based Parallel Systems: Architectural Alternatives And Their Impact

Multidestination message passing has been proposed as an at tractive mechanism for efficiently implementing multicast and o ther collective operations on direct networks. However, applyi ng this mechanism to switch-based parallel systems is non-trivial . In this paper we propose alternative switch architectures wit h differing buffer organizations to implement multidestination wo rms on switch-based parallel systems. First, we discuss issues re lated to such implementation (deadlock-freedom, replication mech anisms, header encoding, and routing). Next, we demonstrate how an e xisting central-buffer-based switch architecture support ing unicast message passing can be enhanced to accommodate multidestin ation message passing. Similarly, implementing multidestinati on worms on an input-buffer-based switch architecture is discussed . Both of these implementations are evaluated against each other as w ell as against a software-based scheme using the central buffer or ganization. Simulation experiments under a range of traffic (multi ple multicast, bimodal, varying degree of multicast, and message l ength) and system size are used for evaluation. The study demonstra tes he superiority of the central-buffer-based switch architect ure. It also indicates that under bimodal traffic the central-buffer-ba sed hardware multicast implementation affects background unicast traffic less adversely compared to a software-based multicast impl e entation. Thus, multidestination message passing can easily be applied to switch-based parallel systems to deliver good collectiv communication performance.