Self-Stabilization Testing of LUT-Based FPGA Designs by Fault Injection

New testing methods are required as the complexity of Field Programmable Gate Array (FPGA) designs grow rapidly and time-to-market demands shorten. In this paper we propose a new, physical fault injection method for the test of a system’s self-stabilizing property, that is its intrinsic ability to recover from transient faults. Therefore we inject transient faults in Look-Up Table (LUT)-based FPGA designs by dynamical, partial reconfiguration.