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In the past, the problem of pow er dissipation during test was only a minor issue since the test was performed at a speed lower than the normal operation speed. Con versely,today's circuits are tested at higher cloc k rates, if possible at the circuit's normal clock rate (atspeed testing). Second, the switc hing activit y of the circuit during self-test is signi can tly larger than during normal operation. Therefore, the po w er dissipation during test can be much larger than during normal operations. Circuits ha ve been reported to be burn t during test. Therefore, reducing pow er dissipation during test application becomes an important objectiv e in BIST design. Energy consumption is another critical concern in design and test of portable computing and wireless communication systems. The mark et acceptanceof mobile applications and notebook computers heavily depends on the operation time per battery pack. To enhance battery life, it is v ery important to reduce energy consumptions during on-line testing. Energy conscious BIST can be used e eciently in on-line testing for battery opperated applications. CMOS technologies have very low pow er/energy consumption when signals are not switching. The majority of the energy dissipation in the current day's technology is due to charging and discharging of load capacitance of logic gates, which occurs when logic gates undergo signal transitions. Hence, in order to reduce pow er/energy consumptions in BIST, it is desirable to reduce the switched capacitance during the test mode. Random pattern testing is widely used in BIST because it does not require large memory overhead while ac hievinghigh fault co verage with a limited num ber of input v ectors. Energy consumption during random test is proportional to the product of the test time (test length) and the average dynamic pow er. There are three main objectiv es in BIST design: to minimize test length (test time) to minimize pow er/energy to maximize fault coverage To achieve the BIST objectives, several di eren t test techniques ha ve been proposed. The con ventional w eighted random pattern testing technique (WRP) reduces the test length by optimizing signal probablities (probabilit y that a signal is logic ONE) or weights of the inputs, but it does not consider any reduction of a verage pow er. On the other hand, DS-LFSR [3] reduces the average pow er by operating one of the tw o linear feedbac k shift registers at slo w speed. Ho w ever, it does not reduce the test length. In order to reduce both the test length and average pow er, Zhang and Ro y proposed a low pow er BIST (LPBIST) [2] technique, in whic h both signal probabilities (probabilit y of signal being logic ONE) and activities (probability of signal switching) at the primary inputs are optimized, hence both the average pow er and the test length are reduced signi cantly. For ISCAS benchmark circuits, while the average of po w er reduction b y using DS-LFSR is 19%, the average of po w er reduction b y using LPBIST tec hnique is as high as 73%. Proper sc heduling of test during BIST can also reduce pow er consumption. The po w er constrain ts of a system are de ned for normal operation, during which only a small number of logic blocks are active, while others are idle. During test, if we apply test patterns to all the blocks sim ultaneously , the pow er constrain ts can be easily violated. In order to a void unwanted failures during test, Chou and Saluja [1] proposed a constrained optimzation algorithm for test scheduling, in which the overall test length is minimized with the constraint of pow er limit. They assumed that both test length, fault coverage and po w er are invariant with respect to the scheduling of test. For systems in which di eren t circuit blocks have common primary inputs, the above algorithm cannot be applied, because di erent blocks with common primary inputs may have con icting testabilit y requirements, and the test length or fault co verage can v ary if di eren t circuits are tested simultaneously or independently. Furthermore, although energy consumption and pow er dissipation are v ery crucial issues for portable applications, the above algorithm does not consider any strategies to reduce the energy/pow er during test. In this paper, we propose a no vel test sc heduling approach whic h incorporates the LPBIST technique. F or each circuit bloc k, the pow er dissipation is minimized and the fault coverage is maximized by optimizing the primary input signal probabilities and activities. Although the test length for each circuit block is xed, the o verall test length is minimized by carefully sc heduling test under the constraint of average pow er.In our approac h, the fault co verage and a v erage pow er for a block are no longer xed numbers, and they ma yvary with di erent test schedules. Let us consider a circuit block A in a large system. If block A is tested as a separate block, then the optimization of signal probabilities and activities at inputs of A will not a ect other blocks. Conversely, if the block A is tested parallelly with other blocks, then we can view all the scheduled blocks (including A) as one hierarchical circuit block, and the optimization of signals at the inputs of A will be a ected by other blocks in the hierarchy. The signal probabilities at the primary inputs of the hierarchical bloc k are optimized such that the fault co verage in the bloc k is maxim um, while the primary input signal activities are optimized such that the total average pow er in the hierarc h y block is minimum. The optimal input probabilities and activities can be di erent depending on whether A is tested parallelly with other blocks or tested alone. Hence both the fault co verage and a v erage pow er in bloc kA depends on how the test is scheduled. In summary, proper test scheduling maximizes the fault coverage by optimizing the primary input signal probabilities, minimizes the average power by optimizing the primary input signal activities, and reduces the overall test time because more blocks can be tested simultaneously at any given time instant.

Power Constrained Test Scheduling with Low Power Weighted Random Testing