Large-Scale Circuit Placement: Gap and Promise

Placement is one of the most important steps in the RTL-to-GDSII synthesis process, as it directly defines the interconnects, which have become the bottleneck in circuit andsystem performance in deep submicron technologies. Theplacement problem has been studied extensively in the past30 years. However, recent studies show that existing placement solutions are surprisingly far from optimal. The first part of this tutorial summarizes results from recent optimality and scalability studies of existing placement tools. Thesestudies show that the results of leading placement tools fromboth industry and academia may be up to 50% to 150% awayfrom optimal in total wirelength. If such a gap can be closed,the corresponding performance improvement will be equivalent to several technology-generation advancements. Thesecond part of the tutorial highlights the recent progress onlarge-scale circuit placement, including techniques for wirelength minimization, routability optimization, and performance optimization.