Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication

Multiple clock cycles are needed to cross the global interconnectsfor multi-gigahertz designs in nanometer technologies. Forsynchronous design, this requires the consideration of multi-cycleon-chip communication at the high level. In this paper, we presenta new architectural synthesis system integrated with globalplacement, named MCAS (Multi-Cycle Architectural Synthesis),on top of the recently-proposed Regular Distributed Register(RDR) micro-architecture. The RDR architecture provides aregular synthesis platform for supporting multi-cyclecommunication. Novel architectural synthesis algorithms thatintegrate high-level synthesis with global placement have beendeveloped in MCAS, including scheduling-driven placement anddistributed controller generation, etc. Experimental results showthat our methodology can achieve a clock period improvement of31% and a total latency improvement of 24% on averagecompared to the conventional architectural synthesis flow.