Toggle-masking for test-per-scan VLSI circuits

This paper presents a novel toggle-masking technique that eliminates the switching activity in a circuit under test (CUT) during the scan-shifting in a test-per-scan test. Conventional scannable D flip-flops (DFFs) are modified to ensure that CUT inputs remain unchanged until an entire test vector is loaded, significantly reducing the power dissipation in the CUT. Our experiments on ISCAS85/89 benchmark circuits show that the proposed technique offers an average of 47% savings in average power compared to previous work (S. Gerstendorfer and H. Wunderlich, Proc. Int. Test Conf., pp. 77-84, 1999), and an average of 99% savings in average power and 8% savings in peak power with respect to test-per-scan circuits with conventional DFFs.