Failure factor based yield enhancement for SRAM designs

With increasing chip density, semiconductor memory yield improvement is becoming a task that can only be done collaboratively by test engineers, product engineers, process engineers, and circuit designers. Design-for-manufacturability (DFM) and design-for-yield (DFY) methodologies have an increasing impact on the yield learning of modem silicon chips. However, a major part of a system chip is typically occupied by memories, which dominate the yield of the chip. During chip integration, it is important that we pick the right design of memory cores that will maximize the yield under the specific process technology chosen. Traditionally, yield prediction is only based on layout and defect statistics. In this paper, we propose to estimate the yield with a failure factor. We thus develop a memory failure factor analyzer (FFA), based on that, we can select the memory design that is more suitable for the given process technology. Experimental results show that we can efficiently evaluate the yields of different memory designs for the same specification, so that the most robust one, that results in the highest yield, can be selected.