Combining low-power scan testing and test data compression for system-on-a-chip | Zendy

Anshuman Chandra | Zendy; Krishnendu Chakrabarty | Zendy

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Combining low-power scan testing and test data compression for system-on-a-chip

Author(s) -

Anshuman Chandra,

Krishnendu Chakrabarty

Publication year - 2002

Publication title -

proceedings of the 38th design automation conference (ieee cat. no.01ch37232)

Language(s) - English

Resource type - Conference proceedings

DOI - 10.1109/dac.2001.935497

Subject(s) - golomb coding , test compression , automatic test pattern generation , computer science , dissipation , chip , test data , system on a chip , computer hardware , data compression , shift register , design for testing , power (physics) , low power electronics , coding (social sciences) , volume (thermodynamics) , embedded system , algorithm , engineering , electrical engineering , electronic circuit , artificial intelligence , reliability engineering , telecommunications , image compression , power consumption , mathematics , image (mathematics) , image processing , testability , quantum mechanics , thermodynamics , programming language , statistics , physics

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