On the capacity of bufferless Networks-on-Chip
Author(s) -
Alexander Shpiner,
Erez Kantor,
Pu Li,
Israel Cidon,
Isaac Keslassy
Publication year - 2012
Publication title -
citeseer x (the pennsylvania state university)
Language(s) - English
Resource type - Conference proceedings
DOI - 10.1109/allerton.2012.6483296
Subject(s) - computer science , scheduling (production processes) , power consumption , network on a chip , distributed computing , computer network , parallel computing , power (physics) , mathematical optimization , physics , mathematics , quantum mechanics
Networks-on-Chip (NoCs) form an emerging paradigm for communications within chips. In particular, bufferless NoCs require significantly less area and power consumption, but also pose novel major scheduling problems to achieve full capacity. In this paper, we provide first insights on the capacity of bufferless NoCs. In particular, we present optimal periodic schedules for several bufferless NoCs with a complete-exchange traffic pattern. These schedules particularly fit distributed-programming models and network congestion-control mechanisms. In addition, for general traffic patterns, we also introduce efficient greedy scheduling algorithms, that often outperform simple greedy online algorithms and cannot have deadlocks. Finally, using network simulations, we quantify the speedup of our suggested algorithms, and show how they improve throughput by up to 35 percent on a torus network.
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