Asymmetrical 17-Level Inverter Topology With Reduced Total Standing Voltage and Device Count | Zendy

M. Saad Bin Arif | Zendy; Uvais Mustafa | Zendy; Shahrin Bin Md Ayob | Zendy; Jose Rodriguez | Zendy; Abdul Nadeem | Zendy; Mohamed Abdelrahem | Zendy

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Asymmetrical 17-Level Inverter Topology With Reduced Total Standing Voltage and Device Count

Author(s) -

M. Saad Bin Arif,

Uvais Mustafa,

Shahrin Bin Md Ayob,

Jose Rodriguez,

Abdul Nadeem,

Mohamed Abdelrahem

Publication year - 2021

Publication title -

ieee access

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.587

H-Index - 127

ISSN - 2169-3536

DOI - 10.1109/access.2021.3077968

Subject(s) - aerospace , bioengineering , communication, networking and broadcast technologies , components, circuits, devices and systems , computing and processing , engineered materials, dielectrics and plasmas , engineering profession , fields, waves and electromagnetics , general topics for engineers , geoscience , nuclear engineering , photonics and electrooptics , power, energy and industry applications , robotics and control systems , signal processing and analysis , transportation

Voltage source Multilevel Inverters (MLIs) are vital components for medium voltage and high-power applications due to their advantages like modularity and better power quality. However, the number of components used is significant. In this paper, an improved asymmetrical multilevel inverter topology is proposed producing 17-levels output voltage utilizing two dc sources. The circuit is developed to reduce the number of isolated dc-sources used without reducing output levels. The circuit utilizes six two-quadrant switches, three four-quadrant switches and four capacitors. The capacitors are self-balancing and do not require extra attention, i.e. the control system is simple for the proposed MLI. Detailed analysis of the topology under linear and non-linear loading conditions is carried out. Comparison with other similar topologies shows that the proposed topology is superior in device count, power quality, Total Standing Voltage (TSV), and cost factor. The performance of the topology is validated for different load conditions through MATLAB/Simulink environment and the prototype developed in the laboratory. Furthermore, thermal analysis of the circuit is done, and the losses are calculated via PLECS software. The topology offers a total harmonic distortion (THD) of 4.79% in the output voltage, with all the lower order harmonics being less than 5% complying with the IEEE standards.

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