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Write-Optimized and Consistent Skiplists for Non-Volatile Memory
Author(s) -
Renzhi Xiao,
Dan Feng,
Yuchong Hu,
Fang Wang,
Xueliang Wei,
Xiaomin Zou,
Mengya Lei
Publication year - 2021
Publication title -
ieee access
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.587
H-Index - 127
ISSN - 2169-3536
DOI - 10.1109/access.2021.3077898
Subject(s) - aerospace , bioengineering , communication, networking and broadcast technologies , components, circuits, devices and systems , computing and processing , engineered materials, dielectrics and plasmas , engineering profession , fields, waves and electromagnetics , general topics for engineers , geoscience , nuclear engineering , photonics and electrooptics , power, energy and industry applications , robotics and control systems , signal processing and analysis , transportation
Skiplist as an in-memory index performs pretty well on rapid insertions because there are no rotations or reallocations for rebalancing. The emerging non-volatile memory (NVM) technologies have spurred a deep interest in designing efficient NVM-based skiplist. Because the data written to NVM may be partially updated or reordered by the memory controller, write operations in NVM-based persistent skiplist may suffer data inconsistency in the face of system failures. Moreover, a traditional Redo-Logging-based consistent Skiplist (RLS for short) guarantees data consistency but introduces double NVM writes, which can significantly degrade the lifetime of NVM. In this paper, we propose two write-optimized and consistent skiplists for NVM, called Atomic Skiplist (AS for short) and Atomic and Selective Consistency Skiplist (ASCS for short). AS exploits log-free failure-atomic writes for both the 0th and internal levels of skiplist to avoid double NVM writes of redo-logging. ASCS leverages selective consistency and log-free failure-atomic writes to further reduce NVM writes from index pointers. Compared with RLS, experimental results show that AS and ASCS reduce the number of cache-line flushes by 67.5% and 75%, decrease the insertion latency by 32.3% - 40.9% and 36.2% - 54.2%, degrade the deletion latency by 38.7% - 47.1% and 44.9% - 57.8%, as well as increase insertion throughput by 49.1% and 65.0% and deletion throughput by 65.1% and 80.5%, respectively.

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