Discrete-Time Systems Modeling and Verification With Alvis Language and Tools | Zendy

Marcin Szpyrka | Zendy; Michal Wypych | Zendy; Jerzy Biernacki | Zendy; Lukasz Podolski | Zendy

AI Assistant Blog Pricing

Home ZAIA Blog

Open Access

Discrete-Time Systems Modeling and Verification With Alvis Language and Tools

Author(s) -

Marcin Szpyrka,

Michal Wypych,

Jerzy Biernacki,

Lukasz Podolski

Publication year - 2018

Publication title -

ieee access

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.587

H-Index - 127

ISSN - 2169-3536

DOI - 10.1109/access.2018.2885249

Subject(s) - aerospace , bioengineering , communication, networking and broadcast technologies , components, circuits, devices and systems , computing and processing , engineered materials, dielectrics and plasmas , engineering profession , fields, waves and electromagnetics , general topics for engineers , geoscience , nuclear engineering , photonics and electrooptics , power, energy and industry applications , robotics and control systems , signal processing and analysis , transportation

Alvis is a formal modeling language intended for developing systems consisting of concurrently operating units (real-time, embedded, and distributed systems). This paper describes the timed version of Alvis that is suitable for modeling discrete-time systems. This paper is the first relatively complete description of timed Alvis. We present formal definition and semantics of timed models and the algorithm of labeled transition system generation and introduce the computer software that we developed to support Alvis. All concepts are illustrated by examples.

The content you want is available to Zendy users.

Already have an account? Click here to sign in.

Having issues? You can contact us here

Accelerating Research