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An Imperialist Competitive Algorithm Incorporating Remaining Cycle Time Prediction for Photolithography Machines Scheduling
Author(s) -
Peng Zhang,
Xinming Zhao,
Xia Sheng,
Jie Zhang
Publication year - 2018
Publication title -
ieee access
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.587
H-Index - 127
ISSN - 2169-3536
DOI - 10.1109/access.2018.2878414
Subject(s) - aerospace , bioengineering , communication, networking and broadcast technologies , components, circuits, devices and systems , computing and processing , engineered materials, dielectrics and plasmas , engineering profession , fields, waves and electromagnetics , general topics for engineers , geoscience , nuclear engineering , photonics and electrooptics , power, energy and industry applications , robotics and control systems , signal processing and analysis , transportation
Photolithography machines are the common bottleneck in the semiconductor manufacturing system. The operation constraints in photolithography machines are very complicated, including wafers arriving over time, dedicated machine constraints for critical layers, auxiliary resources’ constraints, and dynamic manufacturing environment. In previous studies, the dynamic manufacturing environment has never been considered, which would make remaining cycle time seriously deviate from the expected value, and then result in the deterioration of scheduling performance. In this paper, an imperialist competitive algorithm incorporating remaining cycle prediction is proposed for photolithography machines’ scheduling problem with the objective of total completion time minimization. A deep autoencoder neural network is presented at first to predict remaining cycle time, responding to the environmental changes. Secondly, an imperialist competitive algorithm in the framework of a rolling horizon strategy is proposed to address the scheduling problem, incorporated with the accurately predicted remaining cycle time. Several procedures are designed to improve the performance of the algorithm. To verify the proposed algorithm, a simulation model of a semiconductor manufacturing system is constructed and numerical tests are conducted in the model. Results show that the algorithm proposed can significantly decrease wafers’ average cycle time.

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