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We propose SoftCorner, which is a novel approach to estimate the worst delay (3σ delay) of a VLSI system. SoftCorner is a modification of deterministic static timing analysis to overcome its tendency to give pessimistic estimates of the system delays when it uses 3σ corner delays for logic gates. The basic idea of SoftCorner is to use corner delays that are relaxed to <;3σ. To select the relaxed gate delays, SoftCorner uses the delay information obtained from the K most-critical paths and then determines the degree of relaxation, and constructs a model that represents the probability that the delay of each logic gate is selected. This probability model is used to guide the selection of gate delays; the worst system delay with relaxed delay criterion can be obtained by running the selection module until the mean of the results converges. SoftCorner can also estimate the system delay at an arbitrary percentile. In experiments, SoftCorner estimated the system delay of benchmark circuits at 99.87th, 95th and 85th percentiles with an average error <;2% compared with the Monte-Carlo (MC) simulation, and produced the estimates 5.89 × 104 times faster than the MC simulation on average.

SoftCorner: Relaxation of Corner Values for Deterministic Static Timing Analysis of VLSI Systems